1. Field of the Invention
The present invention relates to a demodulation circuit of a communication control system for demodulating pulse-width-modulated significant symbols and data received from a dual wire bus line.
2. Description of Related Art
FIG. 1 shows a pulse-width-modulated bit pattern defined by a PWM (Pulse Width Modulation) bit format according to Class B data communication network interface J1850 for example. The region of one bit of the data transferred on the dual wire bus line is comprised of three segmented areas (hereinafter referred to as "time"). Bit 0, as shown in FIG. 1(a), is expressed by H level at the first time 63 and second time 64, and by L level at the third time 65. Bit 1, on the other hand, is given by H level at the first time 63 and by L level at the second time 64 and third time 65 as shown in FIG. 1(b).
The symbol SOF (Start of Frame) indicating a transmission start, as shown in FIG. 1(c), is expressed by a total of 6 times as a pattern having the first, second, third and fourth times 63 to 66 at H level, and fifth and sixth times 67 and 68 at L level. The symbol EOD (End of Data) meaning the end of transmission, as shown in FIG. 1(d), is expressed by three times including the first, second and third times 63, 64 and 65 all at L level. Further, the symbol EOF (End of Frame) indicating the end of a message frame is expressed by 6 times indicating the first, second, third, fourth, fifth and sixth times 63, 64, 65, 66, 67 and 68 all at L levels.
The PWM symbols and the PWM data thus subjected to pulse width modulation are transmitted and received in a message frame format of SAE.J1850, for example, as shown in FIG. 2. Assume that a transmission frame is sent out. First, the transmission start symbol SOF is sent out, followed by the data 43 providing a PWM data of bit 0 or 1, and then the transmission end symbol EOD indicating the end of transmission. In the case where no error is detected in the symbol and data thus transmitted, the receiving party pulse-width modulates and returns a specific address assigned him as an IFR (In Frame Response). An end of frame signal EOF indicating the end of one message frame is sent out, thereby terminating one message frame.
Now, a method for demodulating the PWM symbols and the PWM data shown in FIG. 1 at the receiving end is explained. The bit 0 and bit 1 providing the PWM data shown in FIGS. 1(a) and 1(b) are comprised of three times. The data is sampled at predetermined sampling points t.sub.1, t.sub.2 and t.sub.3 at the times 63, 64 and 65, and assuming that the first time 63 is at H level, the second time 64 at H level and the third time 65 at L level, the bit 0 is obtained as a demodulation data. With regard to the bit 1, a similar sampling operation is performed at sampling points t.sub.1, t.sub.2 and t.sub.3, so that in the case where the first time 63 is at H level, the second time 64 at L level and the third time 65 at L level, a bit 1 is obtained as a demodulation data.
Now, explanation will be made about the demodulation of the PWM data and the PWM symbol at the receiving end. As shown in FIGS. 1(a) and 1(b), a one-bit width covers 24 clocks, and each time region 63, 64 or 65 is comprised of 8 clocks. The first sampling point t.sub.1 is at the fourth clock from the data rise point, the second sampling point t.sub.2 at the 12th clock, and the third sampling point t.sub.3 at the 20th clock, each sampling being performed at the center of a time region.
This is also the case with the transmission start symbol SOF, the transmission end symbol EOD and the frame end symbol EOF. The transmission start symbol SOF and the frame end symbol EOF is comprised of 6 times, with 48 clocks over the PWM symbol width. As shown at the sampling points t.sub.1, t.sub.2, . . . ,t.sub.6, the first, second, . . . , sixth sampling points t.sub.1, t.sub.2, . . . , t.sub.6 are set to the fourth, 12th, 20th, 28th, 36th and 44th clocks respectively from the rise point of the PWM symbol, and a demodulation data is obtained by sampling at the center of each one-time region. With regard to the transmission end symbol EOD, on the other hand, like the bits 0 and 1 shown in FIGS. 1(a) and 1(b), a demodulation data is obtained by sampling at the center of the one time region of the sampling points t.sub.1, t.sub.2 and t.sub.3.
The dual wire bus line has a stray capacitance. In the case where a transfer data with a PWM symbol and a PWM data is sent out on a dual wire bus line, therefore, the potential change of the dual wire bus line is dulled by the stray capacitance, the pull-up resistance and the pull-down resistance, whereby the H and L levels of the PWM symbol and the PWM data undergo a change. As a consequence, the center of each time region of the PWM symbol and the PWM data may fail to coincide with a sampling point, in which case the sampled demodulation data is likely to be inaccurate. For obviating this problem, the current practice is to send out a transfer data including a PWM symbol and PWM data to the dual wire bus line by means of a driver using a transistor of a large driving ability.
FIG. 3 is a block diagram showing a configuration of the receiver and the driver for connecting the communication control system with the dual wire bus line. A transfer data 42 providing the pulse-width-modulated PWM data, for example, from the communication control system not shown is applied through an inverter 40 to the gate of a P-channel MOS transistor 38 on the one hand and directly to the gate of an N-channel MOS transistor 39 on the other. The drain of the transistors 38, 39 is connected to a non-inverted dual wire bus line (hereinafter referred to as Bus.sup.+) 36 and an inverted dual wire bus line (hereinafter referred to as Bus.sup.-) 37. The source of the transistor 38 is connected to a power supply V, and the source of the transistor 39 grounded. The Bus.sup.+ side is grounded through a pull-down resistor 69, and the Bus side connected to the power supply V through a pull-up resistor 70. A receiver 41, on the other hand, includes a comparator for differential operation, with the positive input terminal+connected to the Bus.sup.+ 36 and the negative input terminal to the Bus 37. The data 5 to be demodulated which is an output of the receiver 41 is applied to the communication control system not shown. The Bus.sup.+ 36 holds a stray capacitance 71 and the Bus.sup.- 37 a stray capacitance 72.
Now, the operation of the driver and the receiver will be explained with reference to the timing chart for signals at various parts in FIGS. 4(a) to 4(d). The transfer data 42 to be sent out to the Bus.sup.+ 36 and Bus.sup.- 37 from the communication control system are applied to the gates of the transistors 38, 39 providing drivers. When the transfer data is inverted from L to H level as shown in FIG. 4(a), the transistor 38 turns on and the Bus.sup.+ 36 is raised to the potential of H level as shown in FIG. 4(b). In the process, a delay time 36ta depends on the driving ability of the transistor 38. Then, in the case where the transfer data is inverted from H to L level as shown in FIG. 4(a), the transistor 38 turns off and the Bus.sup.+ 36 becomes the potential at L level as shown in FIG. 4(b). In the process, a delay time 36tb is determined by the values of the pull-down resistor 69 and the stray capacitance 71. The larger the stray capacitance 71, the longer the delay time 36tb.
Also, the transistor 39 turns on when the transfer data 42 is inverted from L to H level as shown in FIG. 4(a), and the Bus.sup.- 37 assumes the potential of L level as shown in FIG. 4(c). In the process, the delay time 37ta is dependent on the driving ability of the transistor 39. Then, assuming that the transfer data 42 is inverted from H to L level as shown in FIG. 4a, the transistor 39 turns off and the Bus.sup.- 37 becomes the potential of H level as shown in FIG. 4(c). In the process, the delay time 37tb is determined by the values of the pull-up resistor 70 and the stray capacitance 72. The potentials of the Bus.sup.+ 36 and Bus.sup.- 37 thus changed are applied to the receiver 41, and the data 5 to be demodulated which provides an output of the receiver making up a comparator for differential operation, as shown in FIG. 4d, is inverted when the Bus.sup.+ 36 and the Bus.sup.- 37 reach a predetermined potential, which output is applied to a demodulation circuit in the communication control system.
Now, the operation for demodulating the output of the receiver 41 is explained. Assume that the transfer data 42 is sent as the transmission start symbol SOF, the bits 0 and 1 in that order as shown in FIG. 5(a). When the transfer data 42 is applied to the transistors 38, 39 constituting drivers, the potential at the Bus.sup.+ 36 is changed as shown in FIG. 5(b) under the influence of the stray capacitances 71, 72 and the resistors 69, 70 as described above, while the potential at the Bus.sup.- 37 assumes an opposite level. The data 5 to be demodulated which is produced from the comparator providing the receiver 41 is inverted at a timing shown in FIG. 5(c) and is applied to the demodulation circuit (not shown). As a result, as shown in FIG. 5(d), the transmission start symbol SOF samples the data 5 to be demodulated, at the sampling points t.sub.1, t.sub.2, . . . , t.sub.6 within its region, the bit 0 at the sampling points t.sub.1, t.sub.2 and t.sub.3 within its region, and the bit 1 at the sampling points t.sub.1, t.sub.2, t.sub.3 within its region, respectively.
In the case where the transmission start symbol SOF, the bit 0 and the bit 1 applied to the demodulation circuit are demodulated at the sampling points due to the sampling clock as shown in FIG. 5(d), as described above, the potential change of the dual wire bus line is dulled under the influence of the stray capacitance, the pull-down resistance and the pull-up resistance of the dual wire bus line. When the width of the H-level section of the bits 0 and 1 and the transmission start symbol SOF applied to the demodulation circuit is more than a predetermined value, therefore, as shown in FIG. 5(d), the sampling point t.sub.5 in the transmission start symbol SOF section, the sampling point t.sub.3 in the bit 0 section and the sampling point t.sub.2 in the bit 1 section are different from the transmission start symbol SOF, the bit 0 and bit 1 sent out to the dual wire bus line. The resulting problem is that the demodulated PWM symbol and the PWM data, even with a driver having a large driving ability, is likely to be undetermined.
In the above-mentioned prior art, the driver consists of the P-channel MOS transistors and the N-channel MOS transistors. However, in the case where the drive consists of bipolar transistors, the same problems occur.